A flip-flop is a logic circuit used in a computer memory. Typically they are used to construct memory registers in the CPU.

A flip-flop is a feedback circuit. What this means is that the output from the circuit cycles back to form part of the input as well. In practical terms this means that the response of the circuit to new input depends on the previous state. This is the property that makes these types of circuits useful as memory.

SR Flip-flop 1

As an example we will look at a basic SR flip-flop. SR stands for Set Reset. The circuit looks like this:


As you can see the circuit is constructed from two NAND gates.

If R=0 and S=1 then NAND gate Y must give a result of 1, as at least one of its inputs is 0. This means that the inputs to X are 1 and 0, so the output from X is 0, as both its inputs are 1.

If R now changes to 1 the output form the circuit will stay the same. This is referred to the "latched" state. (These circuits are sometimes referred to as latches.) It is only when S drops to 0 that the output from X and Y switches. S can then be set back to 1 without changing the output.

So in simple terms we have a circuit that 'remembers' how it is set until it is told to switch, which is how these circuits are used for memory.

Once the switch is completed S is set back to 1 so that R can be set to 0 and 1 to set the latch again.

It is hard to describe these circuits with a truth table, but this diagram summarizes the behaviour of the circuit:


Note that if both S and R are 0 the circuit goes into an undefined state.

NOR gate SR flip-flop

An SR flip-flop can also be constructed with NOR gates.


In this case if R=1 and S=0 then Q must be 0 and notQ must be 1, as shown by the truth table. The latch is set by switching R to 0. The output can be switched by changing S to 1.

Note that the invalid input for the NOR gate flip-flop is R and S both 1.

Invalid states

In each of these examples of flip-flops there is an invalid state. For the NAND gate this occurs when both inputs are set to 0. The result is that both outputs become 1. When S and R are set back to 1 the output becomes unpredictable.

For the NOR gate flip-flopm the same thing happens when both inputs are set to 0.

Gated SR flip-flop

It is sometimes desireable to control when a flip-flop switches. In this case a gate can be used to add an EN or enable input to control when the switch occurs.


When EN is set to 0 the output from the two AND gates will be 0 regardless of the values of S and R, so the output will locked at the current state. When EN is set to 1 the circuit responds as a normal SR NOR flip-flop. So the flip-flop can now be activated and deactivated with the EN signal.

If the EN input is connected to a clock then the circuit is refered to as "clocked SR flipflop".

The enable input could also be used to protect the flip-flop from entering an unstable state by deactivating it.

JK flip-flop 2

The basic SR flipflop suffers from a couple of problems. Firstly there is the invalid state and secondly if the S and R inputs change while the EN is set to 1 the flip-flop may not work propperly. The JK flip-flop (invented by Jack Kilby)


The added circuitry overcomes the problems with the SR flip-flop. The JK flip-flop is the most widely used flip-flop designs.

You can see from the truth table that JK flipflops are always stable.

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